1. Field of the Invention
The present invention relates to a system and method for identifying design errors in integrated circuits, and in particular to a system and method for using a trainable probabilistic model to predict, detect, and recover from design errors in an integrated circuit design and verification process. This invention relates specifically to design error recovery, while the related divisional patent applications referenced above relate to design error prediction and design error detection, respectively.
2. Related Art
Integrated circuits are becoming increasingly complex as the sizes of transistors and circuit traces continue to decrease, thereby allowing the construction of greater numbers of transistors and logic elements in smaller and smaller packages. As the complexity of integrated circuits, such as, for example, microprocessors, microcontrollers, analog-to-digital converters, and digital signal processors, has increased, the time typically allotted from initial design to final production has steadily decreased due to factors such as market demand, competition, and semiconductor manufacturing improvements.
Consequently, the design of sub-components of integrated circuits are often completed in parallel by multiple teams of designers using a variety of design tools. As a result, it is possible for design errors to be introduced into an integrated circuit that may go undetected until late in the. design process, or possibly not even until after release of a production circuit. Further, the cost of corrective action in addressing design errors typically increases dramatically as circuit design nears completion, and may be most expensive following completion of design and production.
The problem of integrated circuit design error detection has been addressed in several ways. For example, one technique uses a probability network to analyze circuit performance after completion of circuit design to detect manufacturing errors in emitter and base resistors in a VLSI circuit. However, this technique does not apply to other stages or steps of the VLSI circuit design. Further, other types of logic errors are not addressed by this technique.
In another approach, a fault-simulation based technique is used to identify erroneous signals in a VLSI circuit by that can be corrected by re-synthesis of the erroneous signals. The fault-simulation of this technique generates erroneous vectors by random simulation. The erroneous vectors are binary or three valued input vectors that can be used to differentiate between a signal as implemented in a VLSI circuit, and the signal as specified in the circuit design. The correcting power of a particular signal is measured in terms of the signal s correctable set, namely, the maximum set of erroneous input vectors that can be corrected by re-synthesizing the signal. Only the signals that can correct every erroneous input vector are considered as a potential error source. This technique deals with circuit level signal errors, and not design errors, or errors introduced by design tools or methods of design.
In a similar approach, a fault-simulation based technique is used to identify erroneous signals in a sequential VLSI circuit by that can be corrected by re-synthesis of the erroneous signals. This technique locates an erroneous signal in a specific class of logic design errors, and provides a methodology to test whether an incorrect signal can be fixed by re-synthesizing the signal. In other words, this technique provides a method for correcting an erroneous output of a circuit without addressing the root cause of the error. However, re-synthesis of an erroneous signal requires the addition of additional transistors and logic elements to a particular portion of an integrated circuit that is affected by the erroneous signal. Consequently, while re-synthesis of an erroneous signal may fix a specific problem in a circuit, such a fix may introduce other design errors as well as timing and power problems elsewhere in the circuit as a result of the additional transistors and logic elements.
Another technique uses behavioral simulation models to analyze the dependability of a logic circuit early in the design of the circuit. This technique requires that a circuit design be abstracted into a number of discrete levels. The technique then uses the discrete levels to create a behavioral simulation model for performing circuit functional verification, circuit performance evaluation, and circuit dependability analysis. However, because this technique uses a single model, circuit design errors not covered by the model go undetected. Further, where error symptoms are found, there is no mechanism for backtracking to the source of the errors. Finally, this technique is applicable only at early stages of the design.
Still another technique uses a diagnostic algorithm based on backward-propagation techniques to localize design errors in combinational logic circuits. This technique addresses single logic gate replacement and insertion errors. In other words, this technique assumes the existence of a single gate error as the root cause of an error in a logic circuit.
Therefore, what is needed is a system and method for reliably detecting integrated circuit design errors as early in the design process as possible while being capable of detecting errors at any point in the design process. Further, such a system should be capable of detecting multiple types of design errors. The system should be capable of backtracking to the source of an error when error symptoms are detected. The system should also suggest corrective action to address the root cause of the problem as opposed to patching errors to correct deficient or erroneous signals. This invention relates specifically to design error recovery, while the related divisional patent applications referenced above relate to design error prediction and design error detection, respectively.
To overcome the limitations in the related art described above, and to overcome other limitations that will become apparent upon reading and understanding the present application, the present invention is embodied in a system and method for predicting, detecting and recovering from design errors in integrated circuits such as, for example, microprocessors, microcontrollers, analog-to-digital converters, and digital signal processors. For purposes of this description, design errors include errors, such as, for example, errors introduced by improper or incorrect use of design tools, errors introduced by data conversion problems, errors introduced by misinterpretation of design specifications, errors introduced as a result of design methodology, and errors introduced as a result of incorrect or improper logic circuit design or simulation. The system and method of the present invention uses inferential reasoning with a probabilistic model, such as a Bayesian Belief Network (BBN), to predict, detect and recover from design errors at any point in the design process by using information about the current design in combination with historical design data and design error data from previous integrated circuit designs in classes of integrated circuits that are the same or similar as the current design. BBN s are belief based probabilistic models that are typically represented as Directed Acyclic Graphs (DAG) in which nodes represent variables, arcs signify the existence of direct causal influence between the linked variables, and the strengths of these influences are expressed by forward conditional probabilities.
Prediction, detection, and recovery from design errors are preferably based on a probabilistic comparison of conditions or error symptoms, predicted or detected in the current design, to similar or identical conditions or error symptoms associated with design errors identified in prior designs. In addition, the system and method of the present invention are capable of backtracking or rolling back through the design to the source of an error when conditions or error symptoms are predicted or detected, and of rolling forward in a design from the point where conditions or error symptoms are predicted or detected to analyze the effect such conditions or symptoms may have on the overall design functionality and performance, and to determine whether such conditions and symptoms are actually caused by or will produce design errors. The system and method of the present invention also preferably alerts users and suggests corrective action such as, for example, adjusting design attributes, repeating design steps, or suggesting workarounds to be applied to current or future design steps, to address the root cause of predicted and detected design errors in order to recover from those errors.
Identification of design errors as early in the design process as possible is important in order to minimize the cost of redesign. The cost of integrated circuit redesign typically increases as the design nears completion. Consequently, a dynamic probabilistic dependency model having a plurality of conditionally related variables, such as, for example a BBN, is used to predict, detect and recover from design errors. The probabilistic model is preferably displayed both textually and graphically on a computer display device, such that a user may have an immediate visual indication of the present state of the design. In addition, the present invention preferably provides the user with the capability to query the model, input new data into the model, and refine the model by editing or updating data, attributes of the design, probabilities associated with attributes, and confidence factors of the model.
Specifically, the present invention uses inferential reasoning in combination with a dynamic probabilistic model, such as a BBN, to predict, detect, and recover from design errors. The design process is preferably partitioned into a set of tasks, tools, and outputs. Tasks are defined as design efforts by one or more integrated circuit designers using one or more tools to design or develop specific functional units within an overall design. Tools are defined as computer programs or methods used to design or develop specific functional units within an overall design. Outputs at each stage of the design are the final results produced by a combination of tasks and tools at each stage. Design errors are typically introduced into a design by tasks, tools, and integrated circuit designers who utilize, initialize, adjust and interpret various software and hardware tools.
Conditions such as predicted or observed system behavior are analyzed using a probabilistic model, such as a BBN. These conditions are introduced into the design by tasks, tools and integrated circuit designers, and can appear, and be observed, measured, or controlled at any stage of the design. Conditions can create symptoms, which once identified, are preferably traced to design errors. While symptoms are directly related to at least one design error, they may or may not be directly observable or measurable. Consequently, the existence of symptoms is preferably inferred using conditional probabilities generated by the probabilistic model, then traced back to the specific design error or conditions causing the symptoms, again using inferential reasoning in combination with the conditional probabilities generated by the probabilistic model.
Prediction of design errors before observation or measurement of such errors is extremely valuable in that it allows integrated circuit designers to address design errors as early in the design process as possible. Error prediction in accordance with the present invention preferably analyzes a plurality of design environment data, such as, for example, seemingly negligible deviation and warning messages, and infers probabilistic relationships between the design environment data and design error classes, objects, and error templates. The conditions and symptoms associated with a design error in an existing design are input into the probabilistic model of the present invention to predict the probability of the same or similar design errors in a new design. In other words, a probabilistic knowledge-base of historical design errors in a given design environment is used to simulate and infer the existence or probability of occurrence of the same or similar design errors in a new design, at a specific stage or level of that design, before the design is complete. The results of the probabilistic prediction of design errors are preferably presented to the user both textually and graphically in an interactive computer program environment, having elements such as, for example, voice activated input or control, touch screen activated input or control, or input or control activated via a keyboard or pointing device.
Detection of design errors in evolving or completed designs is accomplished by the present invention by monitoring conditions, or patterns of conditions produced by design tasks that have historically been associated with symptoms related to design errors in previous designs. The probabilistic model of the present invention uses fuzzy inferencing to identify and rank condition sets of the present design against historical conditions and condition sets from prior designs. Consequently, where an exact match between present and historical conditions or condition sets is not identified, the inexact pattern matching afforded by inferential analysis of the conditional probabilities generated by the probabilistic model of the present invention is utilized to identify the probability that the same or similar design error exists in the present design as were identified in the prior design. The results of the probabilistic detection of design errors are preferably presented to the user both textually and graphically in an interactive computer program environment.
Recovery from design errors is typically a time consuming and expensive process. However, it has been observed that the same or similar classes of design errors tend to recur often, especially in families, of logic circuits, such as, for example, a microprocessor design that evolves over a period of months or years, and is typically produced and released in incrementally expanded versions. Consequently, the probabilistic model of the present invention provides guidance in addressing and resolving design errors. Specifically, once conditions leading to the symptoms associated with design errors are predicted or detected, a case is generated. An inference engine then uses the conditional probabilities produced by the probabilistic model of the present invention to compile a set of exact or similar cases from a historical knowledge base containing solutions and known fixes to previously identified design errors, based on their probability of matching the case of the current design. These probabilistic cases are then presented to the user, ranked with their likelihood or probability of match to the current predicted or detected design error. These cases are preferably presented to the user both textually and graphically in an interactive computer program environment.
The foregoing and still further features and advantages of the present invention as well as a more complete understanding thereof will be made apparent from a study of the following detailed description of the invention in connection with the accompanying drawings and appended claims.